The consumer market demands for smaller, thinner, lighter and cheaper electronic devices with more diverse functionality and enhanced performance continues unabated. Chip-scale package (CSP) types and various versions of 3-dimensional (3D) integration of devices such as Silicon-on-Chip (SoC), Silicon-in-Package (SiP), or Package-on-Package (PoP) have been developed to minimize or further reduce package footprint. Wafer level packaging (WLP) techniques reduce manufacturing costs by extending wafer fab batch processes to include device interconnect formation and device protection processes. The shrinkage of pitches and pads at the chip-to-package interface has happened significantly faster than the shrinkage at the package-to-board interface, requiring larger-than-chip sized packages to provide sufficient area to accommodate an increasing number of second level interconnects. In consequence, so-called fan-out WLP (FO WLP) techniques have been developed to overcome limitations in interconnect count by chip size.